1. Field of the Invention
The present invention relates generally to data processing systems and more particularly to increasing the data throughput between a controller, such as a microprocessor and its associated peripheral equipment in a multi-terminal configuration. The invention also relates to a decoding method for time multiplexing the address and data outputs of a microprocessor to increase the data output capability of the microprocessor by increasing the data bit word length.
2. Description of the Prior Art
Many techniques exist in prior art real time digital communications systems in which a central processor performs operations on digital data coupled thereto from peripheral equipment at varying data rates. Such systems may, once communication is established, be automatically terminated once the data is completely transmitted or received, without, however, varying bit-length of the transmitted data words. Such a system is disclosed by U.S. Pat. No. 3,251,040.
It is also recognized by the prior art that the number of words available in the main high speed memory of a computer may be effectively increased by dividing the main memory into sections such that the instruction field may, under certain conditions, be loaded into the data field. One such system, in which the word width is increased, but the transfer rate is not, is described by U.S. Pat. No. 3,786,436.
The concept of accessing a microprocessor memory via a single channel for both data and microinstructions is described by U.S. Pat. No. 3,828,320, in which two discrete channels, one for data and one for address, are multiplexed synchronously to a shared memory to enable the storage to be allocated as data or microinstruction storage. While memory capacity is effectively increased, the data throughput capability remains constant. The interleaving of memory in a computer to maximize memory utilization is also well known, and is disclosed by U.S. Pat. Nos. 3,883,854 and 3,866,180. Additionally, U.S. Pat. No. 3,859,636 describes a technique for directly executing instructions coded in a microprogram instruction code format and stored in the main memory of a microprogram controlled microprocessor. In none of the above-described patents is the data output rate increased by time-multiplexing the output address and data lines of a data processor to increase the data word length decoded therefrom.